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LOW SKEW, 1-TO-8 DIFFERENTIAL/ LVCMOS-TO-LVCMOS FANOUT BUFFER
ICS8308I
GENERAL DESCRIPTION
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer and a member of the HiPerClockSTM family of High Perfor mance Clock Solutions from IDT. The ICS8308I has two selectable clock inputs. The CLK, nCLK pair can accept most differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated transmission lines. The ICS8308I is characterized for 3.3V core/3.3V output, 3.3V core/2.5V output or 2.5V core/2.5V output operation. Guaranteed output and part-part skew characteristics make the 8308I ideal for those clock distribution applications requiring well defined performance and repeatability.
FEATURES
* Eight LVCMOS/LVTTL outputs, (7 typical output impedance) * Selectable LVCMOS_CLK or differential CLK, nCLK inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum Output Frequency: 350MHz * Output Skew: (3.3V 5%): 100ps (maximum) * Part to Part Skew: (3.3V 5%): 1ns (maximum) * Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
CLK_EN Pullup
D Q LE 1
PIN ASSIGNMENT
Q0 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q1 VDDO 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDDO Q2 GND Q3 VDDO Q4 GND Q5 VDDO Q6 GND Q7
LVCMOS_CLK Pullup CLK Pullup nCLK Pulldown CLK_SEL Pullup
Q0
0
Q1 Q2 Q3 Q4 Q5 Q6 Q7
ICS8308I
24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm body package G Package Top View
OE Pullup
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TABLE 1. PIN DESCRIPTIONS
Number 1, 11, 13, 15, 17, 19, 21, 23 2, 10, 14, 18, 22 3 4 5 6 7 8 9 12, 16, 20, 24 Name Q0, Q1, Q7, Q6, Q5, Q4,Q3, Q2 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD VDDO Type Output Power Input Input Input Input Input Input Power Power Pullup Pullup Pullup Pullup Pullup Description Clock outputs. LVCMOS / LVTTL interface levels. Power supply ground. Clock select input. Selects LVCMOS clock input when HIGH. Selects CLK, nCLK inputs when LOW. See Table 3A. LVCMOS / LVTTL interface levels. Clock input. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Clock enable. LVCMOS / LVTTL interface levels. Output enable. LVCMOS / LVTTL interface levels. See Table 3B. Core supply pin. Output supply pins.
Pulldown Inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 12 51 51 7 12 Maximum Units pF pF k k
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 Clock Input CLK, nCLK is selected LVCMOS_CLK is selected
TABLE 3B. OE SELECT FUNCTION TABLE
Control Input OE 0 1 Output Operation Outputs Q0:Q7 are in Hi-Z (disabled) Outputs Q0:Q7 are active (enabled)
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs CLK_SEL 0 0 0 0 0 0 1 1 LVCMOS_CLK -- -- -- -- -- -- 0 1 CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 -- -- nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 -- -- Outputs Q0:Q7 LOW HIGH LOW HIGH HIGH LOW LOW HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 70C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 46 11 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3. 3 2. 5 Maximum 3.465 2.625 46 10 Units V V mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD, VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 Typical 2. 5 2. 5 Maximum 2.625 2.625 43 10 Units V V mA mA
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TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85
Symbol Parameter VIH VIL IIN V OH VOL VPP Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 LVCMOS LVCMOS_CLK CLK_EN, OE VIN = VDD or VIN = GND IOH = -24mA IOL = 24mA IOL = 12mA 2.4 0.55 0.30 1.3 VDD - 0.85 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 0.8 300 Units V V 0.8 A V V V V V
Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH.
TABLE 4E. DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter VIH VIL IIN V OH VOL VPP Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 LVCMOS LVCMOS_CLK CLK_EN, OE VIN = VDD or VIN = GND IOH = -15mA IOL = 15mA 1.8 0.6 1.3 VDD - 0.85 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 0.8 300 Units V V V A V V V V
Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; CLK, nCLK GND + 0.5 VCMR NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH.
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TABLE 4F. DC CHARACTERISTICS, VDD, VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter VIH VIL IIN V OH VOL VPP Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 LVCMOS LVCMOS_CLK CLK_EN, OE VIN = VDD or VIN = GND IOH = -15mA IOL = 15mA 1.8 0.6 1.3 VDD - 0.85 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 0.7 300 Units V V V A V V V V
Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; CLK, nCLK GND + 0.5 VCMR NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85
Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical Maximum 350 4 4 100 1 0.2 45 1 55 5 Units MHz ns ns ps ns ns % ns ns ns ns ns ns
350MHz 350MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 0.8V to 2V 150MHz, Ref = CLK, nCLK
2 2
t sk(o) t sk(pp) tR / tF odc tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 4, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK Setup Time; tS CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical Maximum 350 4 4 100 1 0.2 45 1.0 55 5 Units MHz ns ns ps ns ns % ns ns ns ns ns ns
350MHz 350MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 0.6V to 1.8V 150MHz, Ref = CLK, nCLK
2 2
t sk(o) t sk(pp) tR / tF odc tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 4, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK Setup Time; tS CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40 TO 85
Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical Maximum 350 4.2 4.4 160 2 0.2 40 1.0 60 5 Units MHz ns ns ps ns ns % ns ns ns ns ns ns
350MHz 350MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 0.6V to 1.8V 150MHz, Ref = CLK, nCLK
1.5 1. 7
t sk(o) t sk(pp) tR / tF odc tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE 3, 7 Par t-to-Par t Skew; NOTE 4, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK Setup Time; tS CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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PARAMETER MEASUREMENT INFORMATION
1.65V5%
2.05V5% 1.25V5%
VDD, VDDO
Qx
SCOPE
VDD VDDO
GND Qx
SCOPE
LVCMOS
GND
LVCMOS
-1.65V5% -1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V5% VDD
VDD, VDDO
Qx
SCOPE
nCLK
V
PP
Cross Points
V
CMR
LVCMOS
GND
CLK
GND -1.25V5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
DDO
Qx
2
PART 1 Qx
V
DDO
2
V
DDO
Qy
2 tsk(o)
PART 2 Qy
V
DDO
2 tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
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2V
VDD = VDDO = 3.3V
2V 0.8V
Clock Outputs
0.8V tR tF
LVCMOS_ CLK nCLK CLK
VDDO 2
1.8V
VDD = VDDO = 2.5V or
1.8V
VDD = 3.3V, VDDO = 2.5V
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
V
DDO
Q0:Q7 t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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Clock Outputs
0.6V tR
0.6V tF
Q0:Q7
tPD
VDDO 2
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK INPUT For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached.
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
BY
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SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8308I. In this example, the LVCMOS_CLK input is selected. The decoupling capacitors should be physically located near the power pin.
VDD
Zo = 50 Ohm R1 43
R9 1K VDD
R10 1K
R12 1K
VDD VDD U1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 R8 43 3.3V LVCMOS/LVTTL
Ro ~ 7 Ohm
Zo = 50 Ohm 43
R11 3.3V_LVCMOS
VDD=3.3V (U1,9) VDD (U1,12) (U1,16) (U1,20) (U1,24)
Q0 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q1 VDDO
VDDO Q2 GND Q3 VDDO Q4 GND Q5 VDDO Q6 GND Q7
Zo = 50 Ohm
C1 0.1u
C2 0.1u
C3 0.1u
C4 0.1u
C5 0.1u
ICS8308I 3.3V LVCMOS/LVTTL
FIGURE 3. ICS8308I LVPECL BUFFER SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
200
63C/W
500
60C/W
TRANSISTOR COUNT
The transistor count for ICS8308I is: 1040
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PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
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TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8308AGI ICS8308AGIT ICS8308AGILF ICS8308AGILFT Marking ICS8308AGI ICS8308AGI ICS8308AGILF ICS8308AGILF Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube tape & reel tube tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev A T4B T4E T 5B T8 Table Page 11 1 3 4 6 8 14 1 10 14 1 2 Description of Change Added Schematic Layout Features section - added mix supply voltage bullet. Added Mix Power Supply Table. Added Mix DC Characteristics Table. Added Mix AC Characteristics Table. Added Mix Output Load AC Test Circuit Diagram. Ordering Information Table - added "Lead-Free" par t number. Corrected Block Diagram, added CLK_SEL. Added "Recommendations for Unused Input and Output Pins". Ordering Information Table - added Lead-Free note. Pin Assignment - corrected package information from 300-MIL to 173-MIL. Added OE Select Function Table. Date 4/16/04
B
10/20/04
B B
1/12/05 7/25/05 8/4/06 10/16/07
T8 B B T3B
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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